1. Field of the Invention
The present invention relates to an ESD protection device and a circuit thereof, and more particularly, to an ESD protection device with a silicon-controlled rectifier (SCR) and circuit thereof.
2. Description of the Prior Art
Electrostatic discharge (ESD) represents one of the main threats to reliability in semiconductor products, especially in scaled-down CMOS technologies. Due to low breakdown voltage of thinner gate oxide in deep-submicron CMOS technologies, an efficient ESD protection circuit must be designed and placed on every input pad to clamp the overstress voltage across the gate oxide of the internal circuit. The ESD robustness of the ESD protection circuit is generally needed to be higher than 2 kV in the human-body-model (HBM) ESD stress. While withstanding ESD overstress, it is desired that the ESD protection circuit have relatively small dimensional requirements to save silicon area.
A silicon-controlled rectifier (SCR) is demonstrated to be suitable for ESD protection design, because it has both high ESD robustness and low parasitic capacitance under a small layout area. Refer to FIG. 1 and FIG. 2. FIG. 1 is a schematic diagram illustrating a cross-sectional view of a SCR device according to the prior art, and FIG. 2 is a schematic diagram illustrating the current-voltage characteristics of the SCR device according to the prior art. As shown in FIG. 1, the SCR device 10 of the prior art includes a P-type substrate 12, a N-type well 14 disposed in the P-type substrate 12, a first N-type doped region 16 and a first P-type doped region 18 disposed in the N-type well 14, and a second N-type doped region 20 and a second P-type doped region 22 disposed in the P-type substrate 12. When the SCR device 10 is used as a power-rail ESD clamp circuit electrically connected between a high power node 24 and a low power node 26, the first N-type doped region 16 and the first P-type doped region 18 are electrically connected to the high power node 24, and the second N-type doped region 20 and the second P-type doped region 22 are electrically connected to the low power node 26. The SCR device 10 can provides a discharging path to discharging the ESD current zapped from the high power node 24 or the low power node 26, and the discharging path is constituted by the first P-type doped region 18, the N-type well 14, the P-type substrate 12 and the second N-type doped region 20. When an ESD event occurs, the ESD current can be discharged through the discharging path, so that an internal circuit connected between the high power node 24 and the low power node 26 can be protected.
As shown in FIG. 2, the SCR device 10 of the prior art has a trigger voltage Vt and a holding voltage Vh. The trigger voltage Vt of the SCR device 10 is approximately equal to the breakdown voltage of the P-N junction between the N-type well 14 and the p-type substrate 12, about 30-40 volts, and the holding voltage Vh of the SCR device 10 is about 1.2 volts. During the ESD event, the ESD zapping voltage is larger than a trigger voltage Vt of the SCR device 10, so that the discharging path is turned on, and the SCR device 10 is in a latch-up state. During a normal operation, the high power node 24 is generally provided with 3.3 volts, and the low power node 26 is grounded, so that the voltage difference between the high power node 24 and the low power node 26 is smaller than the trigger voltage Vt of the SCR device 10. The SCR device 10 is in an off state.
However, noise generated from the internal circuits is often coupled into the P-type substrate 12, and the SCR device 10 is easily triggered into the latch-up state by the noise or leakage current. When the SCR device 10 is triggered on during the normal operation, the actual signals provided to the internal circuit will not be detected correctly, and even the internal circuit is burnt out by the current passing through SCR device 10.
In order to effectively protect the internal circuit, some designs to increase the holding voltage of the power-rail ESD clamp circuit are provided. Because a diode in the forward-biased condition can sustain a much higher ESD level than it can in the reverse-biased condition, one of the designs provides a diode string to be stacked in series from the first P-type doped region to the P-type substrate to increasing the holding voltage of the SCR device. However, the diode string has a plurality of diodes, respectively disposed in an N-type well. For this reason, each diode, each N-type well and the P-type substrate constitute a PNP bipolar junction transistor (BJT), and the PNP BJTs have common collectors being electrically connected between the high power node and the lower power node. Furthermore, a junction leakage current generated in the P-N junction of the PNP BJT will be amplified by the Darlington pair formed by the PNP BJTs. Therefore, the PNP BJTs still generates large leakage current, and the leakage current may degrade or burn out the internal circuit.